This invention relates to methods for fabricating electrical contacts to regions formed in a semiconductor substrate.
It is known in the art to connect metal (the term "metal" colloquially including conductive materials such as polycrystalline silicon) to various doped regions within a semiconductor substrate. FIG. 1a is a cross sectional diagram of a double diffused MOS ("DMOS") transistor constructed in accordance with the prior art. (A DMOS transistor is one in which the difference in the diffusion of sequentially introduced impurities from a common edge or boundary is used to define channel length.) Transistor 10 of FIG. 1a includes an N+ drain 12d diffused into an N type substrate 14. Included in the N-type substrate 14 is a P region 16. Within P region 16 is an N+ source 12s. Located above a portion of P region 16 is a layer of gate insulation 18 and above gate insulation 18 is a polycrystalline silicon gate 12g. As is well known in the art, when a voltage above the threshold voltage of transistor 10 is applied to gate 12g, current is permitted to flow between source 12s and drain 12d. Illustrated in FIG. 1 a is a metal contact 22 and a metal contact 24. Metal contact 24 makes electrical connection to source region 12s and P region 16 while metal contact 22 makes electrical connection to drain 12d. A third metal contact (not shown) makes electrical contact to polycrystalline silicon gate 12g. (Although FIG. 1a illustrates an N channel DMOS transistor formed in an N type substrate, it is also known to form P channel DMOS transistors in a P substrate.)
A prior art variation of the transistor of FIG. 1a is illustrated in FIG. 1b. Illustrated in FIG. 1b is a transistor 50 including an N+ substrate 52 serving as a drain, located below a more lightly doped N region 54. Within N region 54 is a P+ region 56 and adjacent to P+ region 56 is a pair of N+ regions 58 and 60. Although drawn as two regions, in some prior art transistors, N+ regions 58 and 60 form a single continuous region in the surface of the substrate. Regions 58 and 60 form the source for transistor 50. Above a P region 57 (which extends from P+ region 56) is a layer of insulation 62 and layer of insulation 64. Above regions 62 and 64 are polycrystalline silicon gates 66 and 68. Although gates 66 and 68 are drawn as two separate layers, in some prior art transistors, gates 66 and 68 are a single continuous region on the surface of the substrate. Similarly, insulation layers 62 and 64 also form a continuous layer. When the voltage on gates 66 and 68 is above the threshold voltage of transistor 50, current is permitted to flow between drain region 52 and source regions 58 and 60. Illustrated in FIG. 1b is a metal contact 70 which conducts source current from transistor 50. Another metal contact (not shown) makes electrical contact to gate regions 66 and 68. This transistor is known as a vertical DMOS transistor.
As is known in the art, it is desirable to fabricate devices such as transistors 10 (FIG. 1a) and 50 (FIG. 1b) in as small a surface as possible because processed silicon is expensive and the smaller one can make devices having the same performance, the less expensive they will be. Electrical contacts such as metal contact 70 of FIG. 1b, take up a relatively large surface area. The dimensions of a typical electrical contact region are shown in FIG. 1c. As can be seen, a typical electrical contact, e.g. metal contact 70 is 6 micrometers wide for the body contact (i.e., contact to P+ region 56) and an additional 3 micrometers on each side to allow for adequate contact to source regions 58 and 60. Contacts having these dimensions provide a low resistance ohmic contact while allowing for misalignment, lateral diffusions and various effects which are taken into account in calculating the overall dimension of the device (e.g., under etching, over etching, and mask variations). The cell size in a typical DMOS device, therefore, is in the range of 20 micrometers to 40 micrometers. If it is possible to reduce the size of the electrical contacts, the size of the DMOS device can be reduced and therefore the cost of a DMOS device will also be reduced.